Fast Transform and Quantization Architecture with All-Zero Detection and Bit Estimation for H.264/AVC

摘要：

In this paper a fast processing architecture for the transform and quantization of the H.264/AVC, named DQ Engine, is proposed. Compare with the traditional architecture, proposed DQ engine architecture could achieve 2 times fast processing of transform and quantization together with the inverse transform and inverse quantization when the rate-distortion optimization is performed. Moreover, proposed architecture introduced an all-zero block detection architecture which could cut down the redundant processing of the all-zero coefficient blocks.A bit estimation architecture is also introduced into the DQ Engine to fulfill fast estimation of the generated bits.Implementation results show that the proposed architecture could be fulfilled with only 126,728 transistors.

关键词： RDO DCT Quantization VLSI Architecture

作者: Hiroki KUNIYASU Tomoyuki KISHIDA Tian SONG Takashi SHIMAMOTO

作者单位: Graduate School of Advanced Technology and Science, Graduate School of Engineering, Tokushima Univer Computer Systems Engineering, Institute of Technology and Science, Tokushima University,Minami-Josan

会议类型: 国际会议

会议名称: 第三届信号设计及其在通信中的应用国际会议(Proceedings of 2007 International Workshop on Signal Design and Its Applications in Communications IWSDA07)

会议地点: 成都

会议语种:英文

页码: 334-338

在线出版日期: 2007-09-23（万方平台首次上网日期，不代表论文的发表时间）