Chip Package Interaction in Ultra Low-k/Copper Interconnect Technology

摘要：

Low-k dielectric is used in advanced high performance CMOS chips to reduce wiring capacitance and power consumption. To get more benefit the dielectric constant has been constantly reduced, and currently is in the ultra low-k range below 2.5. This is achieved by introducing porosity in low-k dielectric, which often compromises the mechanical properties such as the modulus and fracture toughness. For example, the cohesive strength of a porous dielectric is about a third of that of silicon dioxide. The weak mechanical properties pose challenges from ultra low-k/copper integration to chip packaging. When an ultra low-k/copper chip is packaged and tested in thermal cycling, dielectric can result in cracking and delamination due to the weak mechanical properties. To ensure packaged chip reliability the interaction of chip and package must be studied and understood.

作者: X.H.Liu T.M.Shaw E.G.Liniger M.W.Lane G.Bonilla J.P.Doyle B.W.Herbst D.L.Questad

作者单位: IBM TJ Watson Research Center 1101 Kitchawan Rd, Yorktown Heights, NY 10598 USA

会议类型: 国际会议

会议名称: 第八届电子封装技术国际会议(2007 8th International Conference on Electronics Packaging Technology ICEPT2007)

会议地点: 上海

会议语种:英文

页码: 38-39

在线出版日期: 2007-08-14（万方平台首次上网日期，不代表论文的发表时间）