Cu low k device wire bonding process modeling
As semiconductor industry reaches 90nm technology node and below, Cu low k technology has been widely used in integrated circuits to further reduce RC delay and power dissipation. Due to the intrinsic properties of low K material (poor adhesion with metal layer, lower modulus and higher CTE), wire bond process window gets narrowed. Crack /peeling between Low k ILD layer and metal (barrier) layer are common wire bond defects which cause both packaging manufacturability and product reliability issues. In this paper,physical and mathematical models of wire bonding process were established. The regression equation of impact force and C/V (Contact Velocity) was obtained through simulation and actual wire bonding data. A Cu Low K CMOS90nm test vehicle was chosen for the modeling. The bonding impact load curve was obtained through the regression of modeling and actual bonding response. The effect of impact force on the formation of smashed ball as well as the mechanical deformation imposed to the bond pad was studied. Through simulation, Capillary dimension-ICA (Inner Chamfer angle)was found critical to achieve 25％ BBR (Ball height to ball size ratio) with 40um BPO (Bond pad opening) which is important for consistent IMC formation and stronger IMC integrity over heat excursion. Through the bond pad deformation simulation under different metal structure design,it is found local low K dielectric design can effectively reduce the bond pad deformation & cupping, thus widen the wire bond process window.
ICA (Inner Chamfer Angle) BBR (Ball Height to Ball Size Ratio).
ZhiJie Wang Vito Huang SuYing Yao ZhiLi He Y.W.Jiang C.L.Zhang Peline Cao
Freescale Inc Institute of Electronic s & Information Engineering, Tianjin University, Tianjin 300381, China Tianjin first middle school
国际会议
第八届电子封装技术国际会议(2007 8th International Conference on Electronics Packaging Technology ICEPT2007)
上海
英文
234-239
2007-08-14（万方平台首次上网日期，不代表论文的发表时间）