Board Level Drop Test Simulation for an Advanced MLP
Handheld electronic products are more prone to being dropped during their lifetime of use. Therefore, the reliability performance of these products during a drop impact has become a concern. Although a new board level test method has been standardized through JEDEC (JESD22-B111),characterization tests are usually expensive and time consuming to complete. In order to reduce costs and the design cycle, many efforts have been made to study the reliability performance under drop impact loading by numerical modeling. In this paper, the implicit Input-G method is adopted to simulate the board level drop test of an advanced molded leaded package (MLP) by using a commercial FEA code. Parametric study on package location at the test board, solder joints height and MLP package thickness is conducted in the board level drop test simulations.The peeling stress and first principle stress of the solder joints are checked and compared. Simulation results show that when the thickness of the package increases the solder joint becomes weaker. Similar trends are obtained for the solder joints height, i.e., lower solder joints are more reliable during the board level drop test.
Yumin Liu Yong Liu Scott Irving
Fairchild Semiconductor Corp., 1 Sutong Road, Suzhou, Jiangsu, P.R.China 215021
国际会议
第八届电子封装技术国际会议(2007 8th International Conference on Electronics Packaging Technology ICEPT2007)
上海
英文
680-684
2007-08-14（万方平台首次上网日期，不代表论文的发表时间）