An Integration of Polyphase Filter and Polyphase Mixer Architecture for High-speed DDC

摘要：

In this paper, a new architecture is proposed for high-speed Digital Down Conversion (DDC) for communication signal processing. The proposed architecture integrates conventional Polyphase Filter with Polyphase Mixer (PFPM) for decimation in DDC. The PFPM architecture decreases both the rate of the mixer and filter and can process the signals with a very high sample rate, which cannot be realistically implement in conventional DDC in a General Purpose Processor (GPP) such as Field Programmable Gate Array (FPGA) or Digital Signal Processor (DSP). Simulation and experiment have been done to verify the availability of the PFPM architecture. These results show that the proposed PFPM architecture reduces the operation rate of the mixer and well agrees with the conventional DDC architecture.

作者: LiuQing PengHong

作者单位: School of Optelectronic Information UESTC Chengdu, Sichuan, China School of Communication and Information Engineering UESTC Chengdu, Sichuan, China

会议类型: 国际会议

会议名称: 2007年通信、电路与系统国际会议(2007 International Conference on Communications,Circuits and Systems Proceedings)

会议地点: 日本福冈

会议语种:英文

在线出版日期: 2007-07-11（万方平台首次上网日期，不代表论文的发表时间）