A Triple-controlled DDS-based PLL for 3 to 4 GHz Frequency Synthesis

摘要：

In this paper, a triple-controlled direct digitalsynthesis (DDS)-based phase-locked loop (PLL) for 3 to 4 GHzfrequency synthesis is presented. The architecture has themerits of low spurs, a fast switching speed and high frequencyresolution. It corrects the output of DDS and changes thedivision ratios of two variable frequency dividers in PLL toavoid high level spurs falling in the loop bandwidth of PLL.The additional DAC output is added to the output of the loopfilter to drive the VCO. It provides the PLL with a fastswitching speed. Experiment and measurement results showedthat this type of frequency synthesizer architecture has betterperformance than conventional PLL and can be used in mostapplications of frequency synthesis.

作者: LiuQing ChengXu

作者单位: School of Optelectronic Information UESTC Chengdu, Sichuan, China School of Electronic Engineering UESTC Chengdu, Sichuan, China

会议类型: 国际会议

会议名称: 2007年通信、电路与系统国际会议(2007 International Conference on Communications,Circuits and Systems Proceedings)

会议地点: 日本福冈

会议语种:英文

在线出版日期: 2007-07-11（万方平台首次上网日期，不代表论文的发表时间）