Distributed Arithmetic for FIR Filter Design on FPGA

摘要：

This paper presents a Distributed Arithmetic (DA) for highly efficient multiplier-less FIR filter designed on FPGA. First, the theory of the Distributed Arithmetic is described. Furthermore, a modification of the DA based on the look up table (LUT) and filter structure to implement the high-order filter hardware-efficient on FPGA is introduced. The proposed filter has been designed and synthesized with ISE 7.1, and implemented with a 4VLX40FF668 FPGA device. Our results show that the proposed DA architecture can implement FIR filters with the smaller resource usage and similar speed in comparison to the previous DA architecture.

作者: Wang Sen Tang Bin Zhu Jun

作者单位: School of Electronic Engineering University of Electronic Science and Technology of China Chengdu, Sichuan, China

会议类型: 国际会议

会议名称: 2007年通信、电路与系统国际会议(2007 International Conference on Communications,Circuits and Systems Proceedings)

会议地点: 日本福冈

会议语种:英文

在线出版日期: 2007-07-11（万方平台首次上网日期，不代表论文的发表时间）