A Novel Design of DDR-based Data Acquisition Storage Module in a Digitizer

摘要：

A DDR-based data acquisition storage module designed for a high-capacity high sampling rate digitizer is described in this paper. The architecture allows two identical data acquisition channels to record consecutive data streams in two acquisition modes—sequence mode in 256k points and single mode in 64M points per channel—at a sampling rate ranging from 40MSa/s to 400MSa/s. The prototype is accomplished by unique DDR SDRAM controller cores embedded in a FPGA device, long acquisition memories combined with a time interleaved ADC system. Also, a flexible trigger mechanism is imported to the module, which is a crucial component to a digitizer, enabling a precise trigger capture with adjustable pretriggering depth.

作者: Jie Guo Yibing Shi Zhigang Wang

作者单位: School of Automation Engineering University of Electronic Science and Technology of China Chengdu, Sichuan Province, P.R.China

会议类型: 国际会议

会议名称: 2007年通信、电路与系统国际会议(2007 International Conference on Communications,Circuits and Systems Proceedings)

会议地点: 日本福冈

会议语种:英文

在线出版日期: 2007-07-11（万方平台首次上网日期，不代表论文的发表时间）