Power-Gating Adiabatic Flip-Flops and Sequential Logic Circuits

摘要：

In this paper, adiabatic flip-flops with data-retention function are proposed, and a power-gating scheme for adiabatic sequential circuits is presented. The proposed data-retention flip-flops are realized using CPAL (complementary pass-transistor adiabatic logic) circuits. The active enable and refresh enable terminals are added for the power-gating operation of the flip-flops. The flip-flops work in three modes.In active mode, the flip-flops act as usual. In hold mode, the flip-flops hold their state on the internal nodes. In refresh mode, the internal nodes are refreshed with their storage value by enabling power-clocks. The energy dissipation of power-gating adiabatic sequential circuits is investigated for different frequencies using a 1010 adiabatic counter. SPICE simulations show that energy loss of the adiabatic sequential circuits is reduced greatly by using power-gating techniques.

作者: Jianping Hu Dong Zhou Ling Wang

作者单位: Faculty of Information Science and Technology Ningbo University Ningbo, Zhejiang 315211, China

会议类型: 国际会议

会议名称: 2007年通信、电路与系统国际会议(2007 International Conference on Communications,Circuits and Systems Proceedings)

会议地点: 日本福冈

会议语种:英文

在线出版日期: 2007-07-11（万方平台首次上网日期，不代表论文的发表时间）