High-Speed Continuous Time Digitizer Using a Two-Level Multiphase Sampling Technique

摘要：

In this paper, the new architecture of a high-speed continuous time digitizer has been proposed. With the aid of atwo-level multiphase sampling technique, the time digitizer can use only 16 delay cells and DFFs to perform the flash-type conversion of 64-stage interpolation. The time digitizer can obtain 78ps resolution with a reference frequency running at 200MHz. The continuous input clock frequency can be up to 250MHz. The layout area occupies 1.08 mm 2. A novel clock multiplier is also introduced to provide multiphase generation with frequency output range within 640 MHz~1.8GHz.

作者: Chorng-Sii Hwang Chih-Wei Sung Hen-Wai Tsao

作者单位: Department of Electrical Engineering National Yunlin University of Science and Technology Yunlin Cou Graduate Institute of Electronics Engineering National Taiwan University Taipei, 106 Taiwan.

会议类型: 国际会议

会议名称: 2007年通信、电路与系统国际会议(2007 International Conference on Communications,Circuits and Systems Proceedings)

会议地点: 日本福冈

会议语种:英文

在线出版日期: 2007-07-11（万方平台首次上网日期，不代表论文的发表时间）