Modeling the Impact of Input-to-Output Coupling Capacitance on Power Dissipation Estimation in Deep Submicron CMOS Circuits

摘要：

In this paper modeling the impact of input-to-output coupling capacitance on power dissipation estimation in submicron CMOS circuits is proposed. Compared with conventional methods, the proposed model is much accurate because it considers the impact of the input-to-output capacitance on power dissipation estimation. In addition, the proposed model can estimate the impact of coupling capacitance on serial gates. The experimental results show that the proposed model can obtain an considerable improvement in accuracy.

作者: Zhangcai Huang Na Li Sui Huang Yasuaki Inoue

作者单位: Graduate School of Production, Information and Systems, Waseda University 2-7 Hibikino, Wakamatsu, Kitakyushu, 808-0135 Japan

会议类型: 国际会议

会议名称: 2007年通信、电路与系统国际会议(2007 International Conference on Communications,Circuits and Systems Proceedings)

会议地点: 日本福冈

会议语种:英文

在线出版日期: 2007-07-11（万方平台首次上网日期，不代表论文的发表时间）