Timing Driven Layer Assignment Considering Via Resistance and Coupling Capacitance

摘要：

As fabrication technology keeps advancing, many nano effects have become increasingly evident. With the steady increase in the number of metallization levels and the shrinking size of vias, via resistance has increased and affected the wire delay greatly. Furthermore, the wire delay is affected more by coupling capacitance instead of wire self capacitance. These problems must be considered in modern VLSI physical design. Traditional approaches only controlled the amount of vias and coupling, and did not optimize wire delay caused by via resistance and coupling capacitance directly. In this paper, we propose a timing driven layer assignment considering via-induced-delay and coupling-induced-delay simultaneously. First, path based timing analysis is used to find the timing-critical part of a circuit. Second, a via aware timing model is suggested to calculate wire delay. Third, the procedure of layer assignment is guided by a Guiding Factor which decides how to assign a net on an appropriate layer pair for direct delay optimization. Experimental results on benchmark circuits show that timing driven layer assignment is necessary and the proposed greedy algorithm is promising.

作者: Yanming Jia Yici Cai Xianlong Hong

作者单位: Department of Computer Science and Technology, Tsinghua University Beijing P.R.China, 100084

会议类型: 国际会议

会议名称: 2007年通信、电路与系统国际会议(2007 International Conference on Communications,Circuits and Systems Proceedings)

会议地点: 日本福冈

会议语种:英文

在线出版日期: 2007-07-11（万方平台首次上网日期，不代表论文的发表时间）