A Research on IDDT Test Pattern Generation Algorithm Based on Digragh Model

摘要：

According to the CMOS NAND gate model, we present a transient current (IDDT) test pattern automatic generation algorithm based on digraph model in this paper. First, we describe the IDDT path that may be formed of a CMOS NAND gate when inputs change, and build the generation table. Next, we build all IDDT path digraph models by regarding the inputs which can generate IDDT as the IDDT test patterns. Based on it, we present a corresponding IDDT test vectors generation algorithm. The results of experiment demonstrate that this algorithm has good precision and efficiency.

作者: Jiang Shuyan Chen Guangju Xie Xuan

作者单位: School of Automation Engineering University of Electronic Science and Technology of China.Chengdu, 610054, China

会议类型: 国际会议

会议名称: 2007年通信、电路与系统国际会议(2007 International Conference on Communications,Circuits and Systems Proceedings)

会议地点: 日本福冈

会议语种:英文

在线出版日期: 2007-07-11（万方平台首次上网日期，不代表论文的发表时间）