AN FPGA-BASED NEURAL NETWORK DIGITAL CHANNEL EQUALIZER

摘要：

The hardware design of an SCFNN equalizer is presented in this paper.The system it implemented using verilog hardware description language and has been verified with ALTERA Quartus Ⅱ.The original equations in the algorithms have been partly rewritten to simplify the hardware design.It has been observed that several multiplications sharing the common operands are performed serially.By using multiplexers and de-multiplexers to replace the multipliers, we have successfully achieved about 30％ savings on the hardware cost.

关键词： SCFNN Fuzzy logic Nural network Channel equalizer

作者: WAN-DE WENG RUI-CHANG LIN

作者单位: Department of Electrical Engineering, National Yunlin University of Science and Technology, Yunlin 6 Department of Electronic Engineering, Nankai Institute of Technology, Nantou, Taiwan

会议类型: 国际会议

会议名称: 2007 International Conference on Machine Learning and Cybernetics(IEEE第六届机器学习与控制论国际会议)

会议地点: 香港

会议语种:英文

页码: 1903-1908

在线出版日期: 2007-08-19（万方平台首次上网日期，不代表论文的发表时间）