An Efficient Iterative Synchronization Scheme for LDPC-Coded DS-SS Systems Using two Samples per Chip

摘要：

In this paper, an efficient iterative timing and carrier phase recovery scheme is proposed for LDPC-Coded Direct Sequence Spread Spectrum (DS-SS) systems. The received signal after the chip-matched filter is two times over sampled per chip. The characteristics of DS-SS signal and LDPC decoder are explored to make the synchronization scheme efficient and simple in such a low sampling ratio. Three sets of correlation values provided by three correlators with different timing offsets are stored to estimate timing and carrier phase. The estimation is performed once per decoding iteration based on the maximum likelihood theory aided by hard decision obtained from LDPC decoder. The overall complexity of this scheme is very Iow and the performance of the proposed scheme approaches that with the ideal synchronization on AWGN channel.

作者: Liu An Luo Wu

作者单位: School of EECS, Peking University,Beijing, P.R.China, 100871

会议类型: 国际会议

会议名称: 2006年IEEE信息理论国际会议(Proceedings of 2006 IEEE Information Theory Workshop ITW06)

会议地点: 成都

会议语种:英文

页码: 522-525

在线出版日期: 2006-10-22（万方平台首次上网日期，不代表论文的发表时间）