A 3D Analytical Model for Calculating the On-resistance of Integrated VDMOSFET

摘要：

Power Integrated Circuits (PlCs) combine high voltage and/or high current devices monolithically with low voltage control circuits. Since all the contacts of the integrated VDMOSFET are on the top of chip, the calculation of its on-resistance doesnit scale in the same manner as for conventional VDMOSFET. The on-resistance of an integrated VDMOSFET is affected deeply by the placement and number of source ceils. In this paper, a 3D analytical model for calculating the on-resistance of integrated VDMOSFET accurately is developed, and can predict the optimum of placement and number of cells for a minimal specific on-resistance within limited chip area.

关键词： integrated VDMOSFET on-resistance placement optimization model

作者: Hong Hui Han Yan

作者单位: Institute of Microelectronics Technology, Zhejiang University, Hangzhou, 310027, China

会议类型: 国际会议

会议名称: PCIM China 2006(International Conference Power Electronics)(2006年中国电力电子技术国际会议)

会议地点: 上海

会议语种:英文

页码: 98-102

在线出版日期: 2006-03-21（万方平台首次上网日期，不代表论文的发表时间）