The Design of Virtual Low-Voltage Power Line Noise Generator

摘要：

Proposed to apply the virtual instrument way to structure the noise generator,according to the complex features of the noises on the low-voltage power line. It talks about the design of the core circuit. used the CPLD-based DDS to stimulate the PLL frequency synthesiser to form the clock generator. Analyzed the method to suppress the phase-noise and the spurious signals of the frequency-synthesis system, proposed to use the balanced scrambling system to suppress the spurious noises from the phase trncation, solved the difficulties in the broad-band signal coupling.

作者: X H Zhang L Y Zhang B Zou Z L Du

作者单位: Harbin University of Science and Technology, Harbin, China, 150040 Harbin Power Engineering Company Limited, Harbin, China, 150046

会议类型: 国际会议

会议名称: 第四届仪器科学与技术国际会议( 4th International Symposium on Instrumentation and Science and Tcchnology)

会议地点: 哈尔滨

会议语种:英文

页码: 686-690

在线出版日期: 2006-08-08（万方平台首次上网日期，不代表论文的发表时间）