A Novel Bus-based Interconnection Topology For Small-scale Multiprocessor System And SOC Multiprocessor System
This paper presents a novel topology, partial-bus, as an alternative to traditional single/multiple shared bus. Through a discrete-time homogeneous Markov model which analytically calculates throughput, the research compares the performance of partial-bus with that of single/multiple bus.The performance comparison indicates that partial-bus may well be a good alternative to single/multiple bus for small scale and SOC multiprocessor systems. To ensure bus allocations of partial-bus is deadlock-free, a Petri-net based model is also introduced to formally describe bus occupation behaviors in partial-bus and verify the deadlockfree property.
interconnection topology homogeneous DTMC model throughput performance evaluation Petri net
Yunni Xia Hanpin Wang Yu Huang
School of electronics engineering and computer science of Peking University, Beijing, China Beijing, 100871, China
国际会议
杭州
英文
1303-1308
2006-10-12（万方平台首次上网日期，不代表论文的发表时间）