FINFET Device Junction Formation Challenges
Double-gate devices with ultra-thin body are considered the most promising for scaling into the sub-20nm regime because of their steeper sub-threshold slope, reduced short channel effects, improved mobility, and drive current. The FinFET device structure is an attractive double-gate structure and most compatible with todays standard processing technologies. One of the challenging issues of fabricating FinFETs device is how to form the FinFETs source-drain junction in the Fin area and develop metrology techniques to measure it. In this paper, we discuss the challenges of implanting ultra-thin fins and metrology development for measuring Fin doping concentration. Our simulation results demonstrate that a high angle of implantation at a certain energy is needed to maximize the dopant distribution in the Fin. Raman microscopy has been developed as a Fin doping measurement metrology. To ease the junction diffusion under the gate and reduce off current dispersion, a gate-source/drain underlap FinFET structure is investigated to make FinFET junction formation more manufacturable. Our simulation data yields optimal characteristics and shows robustness to process variation.
Daniel Pham Larry Larson Ji-Woon Yang
SEMATECH Freescale Semiconductor Assignee 2706 Montopolis Drive, Austin, TX 78741 USA
国际会议
The Sixth International Workshop on Junction Technology(第六届国际结技术研讨会)
上海
英文
2006-05-15（万方平台首次上网日期，不代表论文的发表时间）