The junction challenges in the FinFETs device
The emergence of innovative device architectures such as multiple-gate Field-Effect Transistors (FETs) is a promising solution to scale the CMOS technology beyond the 32nm. Nevertheless, structures as FinFETs suffer from specific challenges that need to be solved for making these devices competitive for circuits manufacturing. We show, via the use of calibrated analytical model of double-gate transistors, that the reduction of the parasitic resistance is a key enabler for increasing the dynamic performance of the FinFETs device. We demonstrate that the parasitic resistance is mainly dependent on the contact resistance between the Si fin and the Source/Drain (S/D) silicide. But the device behavior depends also on the Source/Drain Extension (SDE) doping profile, which needs to be conformal all along the fin in order to prevent the increase of the spreading resistance between the channel and the SDE. Conformal junctions are also mandatory to avoid pseudo-planar FETs electrical behavior when the SDE junction of the top of the fin is deeper and higher doped than the sidewalls. The case of the standard ion implantation process is studied to highlight the limits of the ion beam implantation to fulfill the doping requirement of the FinFETs technology.
Damien Lenoble Gerben Doornbos An de Keersgieter Bartek Pawlak Wilfried Vandervorst Malgorzata Jurczak Thomas Skotnicki
STMicroelectronics, Crolles2 Alliance, 850 rue jean Monnet, 38920 Crolles, France Philips Research Leuven, Kapeldreef 75, B-3001 Leuven, Belgium Inter-University Microelectronics Center (IMEC) Leuven, 75, B-3001 Leuven, Belgium
国际会议
The Sixth International Workshop on Junction Technology(第六届国际结技术研讨会)
上海
英文
2006-05-15（万方平台首次上网日期，不代表论文的发表时间）