Properties of Si / SiO2 Interfaces in Vertical Trench MOSFETs
We report on the study of the Si/SiO2 interface of vertical U-shaped trench-gated n+-polycrystalline Si/oxide/Si (UMOS) capacitor gate structure using capacitance-deep level transient spectroscopy (c-DLTS) and capacitance-voltage (CV). The oxide of a UMOS capacitor is three¨Cdimensional-thermally-grown at different temperature 900 0 C-1175 0 C, on sidewall and base of a reactive¨Cion etched silicon surface. High-density mid-gap Si/SiO2 interfacial traps (~10 11 eV -1 cm -2 ) are observed with both holes and electron trapping. The amphoteric nature of traps is argued to arise from the Pb- dangling Si bond defect center. Moreover, a study of UMOSFET channel region using constant¨C amplitude charge pumping (CP), measurements coupled with electrical stressing of the gate oxide in the Fowler-Nordheim (FN) regime, have shown that the oxide edge adjacent to the drain and the oxide/silicon interface therein are the most susceptible regions to damage. SEM revealed non-uniformity in oxide thickness. Finally, enhanced UMOSFETS channel characteristics are observed for rounded-corner trench-bottom geometry in contrast with sharp-corner trench-bottom geometry.
Samia A.Suliman
Department of Engineering Science and Mechanics / Applied Research Laboratory, The Pennsylvania State University, University Park, PA, 16802, U.S.A.
国际会议
The Sixth International Workshop on Junction Technology(第六届国际结技术研讨会)
上海
英文
2006-05-15（万方平台首次上网日期，不代表论文的发表时间）