THE DESIGN OF HIGH-SPEED AND LOW POWER CONSUMPTION BIDIRECTION VITERBI DECODER

摘要：

In this paper, a scheme based on verilog language to implement the high-speed and Iow power consumption bidirectional Viterbi decoder is proposed. Take the (2, 1,8)decoder for example, the process of how to optimize the decoder is analyzed in detail. The simulation results of the decoder are obtained on Cadence NC Simulator, and they can be provided to Synopsys DC synthesis for ASIC design.Experiment Results show that, on the one hand, by decoding in both positive direction and reverse direction, the delay of the Viterbi decoder introduced in this paper is half of the unilateralism decoder, and the decoding speed is greatly improved. On the other hand, by optimizing the area, storage space and the accessing times of memory, the cost of bidirectional decoding is largely reduced and the low power consumption is achieved at the same time.

关键词： Viterbi decoder Verilog HDL Bidirectional High-speed Low power consumption

作者: SONG LI QING-MING YI

作者单位: Department of Electronic and Engineering, Jinan University, Guangzhou 510632, China

会议类型: 国际会议

会议名称: 2006 International Conference on Machine Learning and Cybernetics(IEEE第五届机器学习与控制论坛)

会议地点: 大连

会议语种:英文

页码: 3886-3890

在线出版日期: 2006-08-13（万方平台首次上网日期，不代表论文的发表时间）