Design of Evolvable Hardware Using Adaptive Simulated Annealing
The evolvable hardware technique is based on evolving the functionality and connectivity of a rectangular array of logic cells. In this paper, an adaptive simulated annealing algorithm is proposed for design combinational circuits with 100％ functionality and minimized number of gates.Experiments for five combinational circuits with our method are compared with NGA, MGA, MLCEA and human designs produced by Karnaugh Maps and Quine-McCluskey method.Results show our method can optimize combinational circuits with shorter chromosome structure and is more adaptive for Evolvable Hardware.
Combinational logic circuit Evolvable Hardware Simulated annealing
He Guo-liang Li Yuan-xiang Liu Feng
School of computer Wuhan university, Wuhan 430072 Hubei, P.R.China
国际会议
武汉
英文
1390-1392
2005-09-23（万方平台首次上网日期，不代表论文的发表时间）