High Speed All Digital Symbol Timing Recovery Based on FPGA

摘要：

This paper presents an all digital timing recovery scheme for high speed Modem. Compared to the conventional schemes, which use a VCO to drive A/D sampling clock, the new scheme based on interpolation filter is easy to simulate and implement. In the case which oversampling rate is slightly larger than 2, the new scheme can also give precise timing recovery. So this scheme is very suitable for high symbol rate situation.Firstly, the theory of the asynchronous symbol timing recovery is presented. Then, an implementation scheme of all digital timing recovery is proposed. As a key component, interpolation filter and timing controller are analyzed. Finally, based on the Xilinx Virtex Ⅱ series FPGA xc2vl000-5, an all digital QPSK timing recovery scheme is implemented. Simulation and hardware test results show that the new scheme can efficiently be used when the symbol rate is up to 45Msps.

关键词： Symbol Timing Recovery Asynchronous Sampling Interpolator All Digital High Speed FPGA

作者: Zhang Jian Wu Nan Kuang Jingming Wang Hua

作者单位: Modern Comm.Lab, Dept.of E.E.Beijing Institute of Technology Beijing, China

会议类型: 国际会议

会议名称: 2005年无线通信、网络和移动计算国际会议

会议地点: 武汉

会议语种:英文

页码: 1402-1405

在线出版日期: 2005-09-23（万方平台首次上网日期，不代表论文的发表时间）