Adaptive Test Program Generation for Embedded Microprocessor Core

摘要：

Test program generation is a crucial step in the design verification of microprocessors. Particularly when microprocessor cores are configurable, devising appropriate test cases may be a difficult task. This paper presents a methodology able to induce test programs according to design configuration for minimizing the time to given verification metrics. The methodology is based on an adaptive formal specification model with heuristic knowledge, which can generate test programs according to different configuration of microprocessors architecture, a test generation scheme with the greedy boundary bounce (GBB) algorithm, which can efficiently provide instructions in test programs, and a validation environment, which supports simulation with generated test programs automatically and check the equivalence of processors and the specified instruction reference model. Experimental results show the effectiveness of the approach.

作者: Haihua Shen Lin Ma Zhaojun Wang Heng Zhang

作者单位: Institute of Computing Technology Chinese Academy of Sciences Beijing, China

会议类型: 国际会议

会议名称: 首届嵌入式软件与系统国际会议(Proceedings of the First International Conference on Embedded Software and System)

会议地点: 杭州

会议语种:英文

页码: 472-479

在线出版日期: 2004-12-09（万方平台首次上网日期，不代表论文的发表时间）