Using Model-based Test Program Generator for Simulation Validation

摘要：

The continuous advances in microelectronics design are creating a significant challenge to design validation in general, but tackling pipelined microprocessors is remarkably more demanding. This paper presents a methodology to automatically produce a test program for simulation-based validation of microprocessors maximizing the given verification constraints. The approach integrates an accurate c-simulator to trace internal states, including memory access patterns, cache states, pipeline states and so on, of the target processor to generate test vectors with higher efficiency. The proposed methodology was used to verify an embedded processor with a 7-statge pipeline developed by our team and gained remarkable effects.

作者: Youhui Zhang Jinglei Wang Dongsheng Wang Weimin Zheng

作者单位: Department of Computer Science, Tsinghua University 100084 Beijing P.R.China

会议类型: 国际会议

会议名称: 首届嵌入式软件与系统国际会议(Proceedings of the First International Conference on Embedded Software and System)

会议地点: 杭州

会议语种:英文

页码: 500-505

在线出版日期: 2004-12-09（万方平台首次上网日期，不代表论文的发表时间）