Analog Integrated Circuit Design of a Hypertrellis Decoder
The first integrated analog hypertrellis decoder for a non-binary (5, 4) single check code over Z4 (the integer ring modulo 4) is presented. Computation is performed at 50MHz in cascode current mode for efficient routing, accuracy and speed. Hard decision outputs are generated for efficient testing, while soft outputs are available for accuracy testing. The chip is designed in a 0.5μm Agilent CMOS n-well process and occupies an area of 3.8 mm2.
Hypertrellis Current Mode Analog Decoder
Zong-Qi Hu Wai Ho Mow Wing-Hung Ki
Department of Electrical and Electronic Engineering The Hong Kong University of Science and Technology Clear Water Bay, Hong Kong SAR, China
国际会议
成都
英文
552-556
2003-08-27（万方平台首次上网日期，不代表论文的发表时间）