Mapping Data-Flow Graph to Loop Engine on Array Processor

摘要：

This paper presents a novel architecture for array processor, called LEAP, which is a set of simple processing elements. The targeted programs are perfect innermost loops. By using the technique called if-conversion, the control dependence can be converted to data dependence to prediction variables. Then an innermost loop can be represented by a data dependence graph, where the vertexsupports the expression statements of high level languages.By mapping the data dependence graph to fixed PEs, each PE steps the loop iteration automatically and independently at the runtime. The execution forms multiple pipelining chains. The simulation of four loops of LFK shows the effectiveness of the LEAP architecture, compared with traditional CISC and RISC architectures.

关键词： array processor chip multiprocessor pipeline chaining

作者: Yong Dou Xicheng Lu

作者单位: National Laboratory for Parallel and Distributed Processing Changsha, Hunan, 410073, China

会议类型: 国际会议

会议名称: Proceedings of The Fourth International Conference on Parallel and Distribyted Computing,Applications and Technologies(第四届并行与分布式计算应用与技术国际会议)

会议地点: 成都

会议语种:英文

页码: 676-680

在线出版日期: 2003-08-27（万方平台首次上网日期，不代表论文的发表时间）