Redundancy Analysis Simulation for Electrical Die Sorting (EDS) Process
It takes about four to five weeks to fabricate a semiconductor memory device. As the fabrication process consists of various operations, there is a possibility of fabricating a final product with defects. It would be impossible for us to repair a memory device if it has numerous defects that cannot be dealt with properly. However, in case of a small number of defects,it is desirable to reuse a defective die (standard unit measuring a device on a wafer) after repair rather than to discard it, because reuse is an essential element for memory device manufactures to cut costs effectively. To perform the reuse, laser-repair process and redundancy analysis for setting an accurate target in the laser-repair process is needed. In this paper, cost reduction was attempted by reducing time in carrying out a new type of redundancy analysis after simulating each defect.
redundancy analysis correlation electrical die sorting process fail bit map
Youngshin han Junho Suh Chilgee Lee
School of Information and Communication Engineering SungKyunKwan University 300, Chunchun-dong, Jangan-gu, Suwon, Kyunggi-do 440-746, S.Korea
国际会议
成都
英文
757-761
2003-08-27（万方平台首次上网日期，不代表论文的发表时间）