A CMOS Display Port/HDMI Dual Standard Transmitter Chip for Next Generation Video Display Interfacing
A CMOS video interfacing chip supporting both DisplayPort and HDMI/DVI standards has been designed and manufactured. Fig. 1 shows the functional diagram of the integrated chip. It operates at DisplayPort high rate 2.7Gb/s and reduced rate 1.62 Gb/s with 1x, 2x and 4-x lane configuration. It also supports 250Mb/s to 2. 25Gb/s HDMI data transfer (1.65 Gb/s for DVI). Both DDR and SDR are supported at the video inputs with RGB 6 -/8 -/10-bit color depth, and YCbCr 422/444 8 -/10-bit color component. A delay-locked loop is implemented to support high speed DDR interfacing up to 700Mb/s. At the core, DisplayPort link layer and physical coding sub-layer (PCS) are integrated together with HDMI/DVI data packing and TMDS encoding. GPU interface and configuration unit helps the software development in GPU and link management if necessary. At physical media side, an innovative clock generation unit is designed to generate high speed clock with good jitter performance. Physical media signaling levels have been tightly controlled with programmable pre-emphasis adjustment. The key performances are summarized as follows.
Mark Qu Ding Lu
Parade Technologies, Inc., 530 Lakeside Dr. , Ste. 230, Sunnyvale,CA94085 USA
国际会议
上海
英文
208-209
2007-03-12（万方平台首次上网日期，不代表论文的发表时间）