A High Performance Memory System for Video Display

摘要：

To display video stream smooth, off-chip memory access is crucial factor in motion compensation and display feeder. This paper proposes a novel memory system architecture, based on motion vector analysis, for video display, which reduces more than 60％ cycle number. The efficient memory access style for display feeder ensures sufficient data transfer bandwidth. And, the special memory system keeps data undisturbed with each other. Accordingly, a special local AMBA, used only for reference frame makes memory access at high speed, and dual memory controllers make bus efficient. Experiment results show that the design supports 30 fps real-time digital-HDTV 720 p clocking at 60 MHz.

关键词： Memory System Video Display Bandwidth H.264/AVC

作者: Nairan Zhang Ligang Hou Wuchen Wu

作者单位: VLSI & System Lab, Beijing University of Technology Beijing 100022, China

会议类型: 国际会议

会议名称: 2007亚洲显示国际会议（AD07）

会议地点: 上海

会议语种:英文

页码: 2060-2065

在线出版日期: 2007-03-12（万方平台首次上网日期，不代表论文的发表时间）