Bit-Level Parallel Array Algorithms of Vector-Vector and Matrix-Matrix Multiplication

摘要：

Based on Horner rule and Baugh-Wooley algorithm, this paper presents two novel bit-level parallel array algorithms of 2s complement multiplication, and the algorithms have been mapped to systolic arrays by using linear mapping techniques. We propose two efficient systolic arrays of multiply and accumulate (MAC) operation and we also describe the vector-vector and matrix-matrix multiplication that can be efficiently implemented by using the MAC arrays. The two systolic arrays have high performance (low time complexity, space complexity and latency) and consume smaller gate-area in comparison to other architectures. It is suitable for VLSI implementation for its regularity and modularity.

作者: Guo Li Wang Miao-feng Qiu Tian Liu Lu Luo Feng

作者单位: Department of Electronic Science and Technology University of Science and Technology of China Hefei 230027, Anhui, P.R.China

会议类型: 国际会议

会议名称: 2006 International Conference on Communications,Circuits and Systems(第四届国际通信、电路与系统学术会议)

会议地点: 广西桂林

会议语种:英文

页码: 567-570

在线出版日期: 2006-06-25（万方平台首次上网日期，不代表论文的发表时间）