Obtaining High Performance Switching with Port Distributed Memories
Output queuing is well known for being able to offer high performance switching. Unfortunately, the high-speed memory requirements of OQ switch limit its use for large capacity switching architecture. Hence a practical manner for large capacity switching architecture to obtain high performance switching is to build novel switch architecture which can emulate output queued (OQ) switch. Most of the presented schemes either still need a mild speedup or need scheduling algorithms with great complexity. In this paper, we build a high performance switch architecture with port distributed memories which is denoted as PDM switch. It is proved by fluid model techniques that the PDM switch can achieve a throughput of 100％ with no speedup when subjected to arbitrary distributed admissible traffic that satisfies the strong low of large numbers (SLLN). Furthermore, we prove that the PDM switch can exactly emulate an output queued (OQ) switch with no speedup, regardless of the incoming traffic pattern. Based on the PDM switch, we present a two stage priority round robin (TSPRR) algorithm. The simulation results illuminate that the PDM switch with TSPRR algorithm can obtain a preferable performance.
Peng Yi Yufeng Li Hui Li Binqiang Wang
National Digital Switching System Engineering & Technology R&D Center (NDSC) Zhengzhou, Henan, P.R.C National Digital Switching System Engineering & Technology R&D Center (NDSC) Zhengzhou, Henan, P.R.C School of Computer & Information Engineering, Shenzhen Graduate School, Peking University Shenzhen,
国际会议
2006 International Conference on Communications,Circuits and Systems(第四届国际通信、电路与系统学术会议)
广西桂林
英文
1686-1690
2006-06-25（万方平台首次上网日期，不代表论文的发表时间）