Design, Implementation and Testing of the Controller for the Terabit Packet Switch

摘要：

The sequential greedy scheduling (SGS) is a scalable algorithm that provides non-blocking in high-capacity packet switches.We implemented the SGS scheduler in the FPGA device, and examined its scalability and speed. Then, we developed the software for design testing. Our testing software confirms the correct functioning of the scheduler. Both, the scheduler implementation, and the testing software are presented in this paper.

作者: Milo(s) Petrovi(c) Milo(s) Blagojevi(c) Aleksandra Smiljani(c) Vladimir Jokovi(c)

作者单位: Belgrade University, Belgrade, Serbia and Montenegro Belgrade University, Belgrade, Serbia and Montenegro;Stony Brook University, New York, USA

会议类型: 国际会议

会议名称: 2006 International Conference on Communications,Circuits and Systems(第四届国际通信、电路与系统学术会议)

会议地点: 广西桂林

会议语种:英文

页码: 1701-1705

在线出版日期: 2006-06-25（万方平台首次上网日期，不代表论文的发表时间）