A 15-bit 10-Msample/s Pipelined A/D Converter Based on Incomplete Settling Principle

摘要：

This paper proposes a 15-bit 10-MS/s pipelined ADC. To implement the incomplete settling principle, the traditional complete settling stage is improved to the incomplete settling structure through dividing the sampling clock of the traditional stage into two parts for discharging the sampling and feedback capacitors and completing the sampling, respectively. It verifies the correction and validity of optimizing ADCs conversion speed without increasing power consumption through the incomplete settling. It is processed in 0.18μm 1P6M CMOS mixed-mode technology. Simulation results show that 82dB SNDR and 87dB SFDR are obtained at the sampling rate of 10MHz with the input sine frequency of 100KHz and the whole static power dissipation is 21.94mW.

作者: Shuaiqi Wang Fule Li Yasuaki Inoue

作者单位: Graduate School of Production,Information and System Waseda University Kitakyushu-shi, Japan Institute of Microelectronics Tsinghua University Beijing, China Graduate School of Production, Information and System Waseda University Kitakyushu-shi,Japan

会议类型: 国际会议

会议名称: 2006 International Conference on Communications,Circuits and Systems(第四届国际通信、电路与系统学术会议)

会议地点: 广西桂林

会议语种:英文

页码: 2176-2180

在线出版日期: 2006-06-25（万方平台首次上网日期，不代表论文的发表时间）