An 8-Bit 250MSPS Modified Two-Step ADC

摘要：

Based on conventional two-step ADC principle, an 8-bit 250MSPS modified two-step ADC is proposed to reduce power dissipation. It is realized by applying triple-stage comparison for the number reduction of comparators, substituting new reference region selecting logic (RRSL) blocks for sub-DACs and adding Sample/Hold (S/H) circuit to replace residue amplifier. Simulated with SMIC 0.35μm/3.3V AMS Si-CMOS process models, the results are shown that on the condition of realizing 250MSPS, the ADC achieves DNL＜±0.4LSB, INL＜±0.5LSB, SFDR 59.2dB at Nyquist frequency, only 85mW power dissipation and 1.2×0.8 mm2 layout area. The ADC system architecture is to be employed in the field of high-speed low-power mixed-signal processing.

作者: Ning Ning Long Fan Shuang-yi Wu Yuan Liu Guo-qing Liu Qi Yu Mo-hua Yang

作者单位: School of Microelectronics and Solid-State Electronics University of Electronic Science and Technology of China Chengdu, Sichuan, China

会议类型: 国际会议

会议名称: 2006 International Conference on Communications,Circuits and Systems(第四届国际通信、电路与系统学术会议)

会议地点: 广西桂林

会议语种:英文

页码: 2197-2200

在线出版日期: 2006-06-25（万方平台首次上网日期，不代表论文的发表时间）