Analysis of FPGA Logic Block Architectures and Functional Improvement of Fine Grained Cells

摘要：

Up to date, many different FPGA logic block architectures,varying in size, functionality and complexity 1, 2, have been proposed. The most common FPGA logic blocks either have multiplexers or look-up-tables (LUTs). This article evaluates the performance of logic block architectures of both kinds. For this purpose, logic cells from leading FPGA vendors are considered along with a few from the academia. A comparative study of number of logic cells required for a particular design, area occupied by a design, speed of implementation and utilization is performed. Based on this study, three novel fine grained logic block architectures have been proposed which show improved performance.

作者: Jun Zheng Rohith Ramnath Yingtao Jiang Mei Yang

作者单位: Department of Computer Science Queens College-CUNY Flushing, NY 11367, USA Department of Electrical and Computer Engineering University of Nevada, Las Vegas Las Vegas, NV 8915

会议类型: 国际会议

会议名称: 2006 International Conference on Communications,Circuits and Systems(第四届国际通信、电路与系统学术会议)

会议地点: 广西桂林

会议语种:英文

页码: 2210-2214

在线出版日期: 2006-06-25（万方平台首次上网日期，不代表论文的发表时间）