Power-Gating Techniques for Low-Power Adiabatic Circuits

摘要：

In adiabatic circuits, the energy dissipation occurs even for constant input signals, as output nodes are always charged and discharged by power-clocks during every cycle. Some adiabatic logic units can be switched off during idle periods to reduce energy loss. This paper presents a new power-gating technique for adiabatic circuits. A power-gating switch with bootstrapped NMOS transistors is used to detach adiabatic logic blocks from power-clocks. The CPAL (complementary pass-transistor adiabatic logic) circuits with the proposed power-gating technique are investigated. SPICE simulations show that energy loss is reduced greatly by shutting down idle adiabatic circuit blocks.

作者: Jianping Hu Tiefeng Xu Ping Lin

作者单位: Faculty of Information Science and Technology Ningbo University Ningbo, Zhejiang 315211, China

会议类型: 国际会议

会议名称: 2006 International Conference on Communications,Circuits and Systems(第四届国际通信、电路与系统学术会议)

会议地点: 广西桂林

会议语种:英文

页码: 2239-2243

在线出版日期: 2006-06-25（万方平台首次上网日期，不代表论文的发表时间）