Low Voltage Low Power Class-AB OTA with Negative Resistance Load
In this paper, a low voltage low power rail to rail class-AB OTA in standard CMOS technology is proposed. The architecture is based on current mirror OTA topology with a local feedback between the output nodes of the first stage. The negative resistance load (NRL) is employed for compensation parasitic resistance of the first stage and the dc gain of the proposed OTA is enhanced. Compared to conventional voltage controlled NRL circuit transistor sizing controlled NRL circuit is used to avoid negative voltage circuits in the proposed OTA. Class AB output stage is implemented to obtain rail to rail output swing and higher slew rate. Using a 0.18-um standard CMOS process, the OTA has been designed to operate with 1V supply voltage. For a load capacitance of 5pf the proposed OTA achieves DC gain of 58.25dB, GBW of 50MHz, phase margin of 61 degrees, and slew rate of 2.3v/uS with a quiescent power consumption of 67uW.
Airong Liu Huazhong Yang
Department of Electronic Engineering Tsinghua University Beijing, China
国际会议
2006 International Conference on Communications,Circuits and Systems(第四届国际通信、电路与系统学术会议)
广西桂林
英文
2251-2254
2006-06-25（万方平台首次上网日期，不代表论文的发表时间）