A Novel Technique for Improving the Linearity of MOS Sampling Switch
A novel technique is proposed to improve the linearity of the MOS sampling switch (SW) by generating a replica transistor with the same threshold voltage as the sampling transistor. And it is obtained by forcing the replica transistor to operate in the triode region with the help of resistive voltage divider. The circuit has been implemented in Chartered 0.35μm standard CMOS technology. The proposed switch achieves a spurious free dynamic range (SFDR) of 110dB for a 30 MHz, 1Vp-p input signal, sampled at a rate of 80MS/s, about 10dB over the conventional switch, and the onresistance variation is reduced by 90％.
Yunfeng Peng Wei Yan Derui Kong Feng Zhou
ASIC & Systems of States Key Lab, Fudan University Shanghai, China
国际会议
2006 International Conference on Communications,Circuits and Systems(第四届国际通信、电路与系统学术会议)
广西桂林
英文
2268-2272
2006-06-25（万方平台首次上网日期，不代表论文的发表时间）