Design of Reconfigurable Low-Power Pipelined Array Multiplier

摘要：

Energy-efficient multiplier is greatly desirable for DSP systems and computer architectures. In many of these systems, the dynamic-range of input operands for multiplier is usually very small. In addition, the least significant bits of output products are often rounded or truncated to avoid growth in word size. Based on these features, this paper presents a low-power and reconfigurable signed pipelined array multiplier that can dynamically detect input range and disable the switching operations of non-effective ranges to decrease the power consumption. Moreover, the proposed pipelined multiplier can be configured to trade output precision with power consumption. Experimental results show that the proposed pipelined multiplier leads to up 40.7％ power saving with a little additional area and delay overheads.

作者: Jiun-Ping Wang Shiann-Rong Kuang Yuan-Chih Chuang

作者单位: Department of Computer Science Engineering National Sun Yat-Sen University Kaohsiung, Taiwan

会议类型: 国际会议

会议名称: 2006 International Conference on Communications,Circuits and Systems(第四届国际通信、电路与系统学术会议)

会议地点: 广西桂林

会议语种:英文

页码: 2277-2281

在线出版日期: 2006-06-25（万方平台首次上网日期，不代表论文的发表时间）