Interconnect Power Optimization Based on the Integration of High-level Synthesis and Floorplanning

摘要：

In this paper, we mainly present a novel approach which is based on the integration of high-level synthesis (HLS) and floorplanning (FP), to solve the problem of optimizing interconnect power of circuit designs. Although many methods have been proposed to deal with the above problem either from the HLS part or from the FP part, none of them makes use of the interactive information between the two procedures to get a better optimization solution. Therefore, our proposed approach takes into account not only the physical information in HLS part, but also the behavioral information while in floorplanning. Experimental results on benchmarks indicate that our design can make an improvement on the total interconnect power dissipation by 15.4％ over the original optimizing method.

作者: Zhipeng Liu Jinian Bian Qiang Zhou Liu Yang Yunfeng Wang

作者单位: Department of Computer Science and Technology Tsinghua University Beijing, P. R. China

会议类型: 国际会议

会议名称: 2006 International Conference on Communications,Circuits and Systems(第四届国际通信、电路与系统学术会议)

会议地点: 广西桂林

会议语种:英文

页码: 2286-2290

在线出版日期: 2006-06-25（万方平台首次上网日期，不代表论文的发表时间）