Floorplanning for Even On-Chip Thermal Distribution
In this paper, we present a floorplanning tool that aims at reducing hot spots and distributing temperature evenly cross a chip while optimizing the traditional design metric, chip area and total wire length. The floorplanning problem is represented by corner block list, and a tool called HotSpot is used to calculate floorplanning temperature based on the power dissipation, the physical dimension, and the location of modules. Area, total wire length and temperature optimizations leading to a multi-objective optimization problem, solved using evolutionary annealing. The experimental results using MCNC benchmarks show that our combined area, wire length and thermal optimization technique decreases the maximal temperature sufficiently while providing floorplans that are as compact as the traditional area-oriented techniques, and no noticeable total wire length increase.
Ning Xu
School of Computer Science and Technology Wuhan University of Technology Wuhan, 430070, P.R. china
国际会议
2006 International Conference on Communications,Circuits and Systems(第四届国际通信、电路与系统学术会议)
广西桂林
英文
2411-2414
2006-06-25（万方平台首次上网日期，不代表论文的发表时间）