Use Augmented Connection Boxes to Improve FPGA Performance

摘要：

With the rapid progress of VLSI technology FPGAs performance efficiency has become the main concern of designers and manufacturers. Our goal in this work is to propose a new FPGA structure to reduce critical net delay without increasing routing area. The augmented connection box is proposed. It allows two different signals to share one track in a connection box by inserting additional switches where logic pins have connection with tracks. The experimental results prove that the augmented connection box improves FPGAs delay performance by avoiding detour when nets are routed. And the possible delay increase incurred by switch addition does not happen. Also channel width is reduced a lot.

作者: Catherine L.Zhou Yu-Liang Wu Wai-Chung Tang

作者单位: Department of Computer Science and Engineering The Chinese University of Hong Kong Shatin, N.T., Hong Kong

会议类型: 国际会议

会议名称: 2006 International Conference on Communications,Circuits and Systems(第四届国际通信、电路与系统学术会议)

会议地点: 广西桂林

会议语种:英文

页码: 2469-2473

在线出版日期: 2006-06-25（万方平台首次上网日期，不代表论文的发表时间）