Calculating the Effective Capacitance for Interconnect Loads Based on Thevenin Model

摘要：

Interconnect wires give large influences on circuit delay in very deep submicron designs. Thevenin model and effective capacitance Ceff concept are usually used to calculate the delay of gate with interconnect loads. In the researches before, the condition that the charges transferred to Ceff and RC-π are not equal was not considered. With the progress of IC process technology, its influence on Static Timing Analysis becomes larger. In this paper, we consider this condition, and propose an new algorithm for calculating the effective capacitance based on Thevenin model. Experimental results show that it is in agreement with the Spice simulation.

作者: Shuai Fang Zhangcai Huang Atsushi Kurokaway Yasuaki Inoue

作者单位: Graduate School of Information, Production and Systems Waseda University, Fukuoka, 808-0135 Japan Semiconductor Technology Academic Research Center (STARC) Yokohama, 222-0033 Japan

会议类型: 国际会议

会议名称: 2006 International Conference on Communications,Circuits and Systems(第四届国际通信、电路与系统学术会议)

会议地点: 广西桂林

会议语种:英文

页码: 2474-2477

在线出版日期: 2006-06-25（万方平台首次上网日期，不代表论文的发表时间）