Efficient Decoder Implementation for QC-LDPC Codes

摘要：

Channel coding is an important building block in communication systems. Low-Density Parity-Check codes is one kind of prominent error correcting codes being considered in next generation industry standards. This paper presents a memory efficient, very high speed decoder architecture suited for Quasi-Cyclic Low-Density Parity-Check codes using modified Min-Sum decoding algorithm. In general, about seventy percent of message memory can be saved over conventional decoder architectures, and the decoding speed can be largely accelerated because of the highly efficient VLSI architecture. Consequently, the proposed approach facilitates the applications of LDPC codes in area/latency sensitive communication systems.

作者: Jin Sha Minglun Gao Zhongjin Zhang Li li Zhongfeng Wang

作者单位: Institute of VLSI design Nanjing University Nanjing, China, 210093 School of EECS, Oregon State University Corvallis, OR 97331-5501, USA

会议类型: 国际会议

会议名称: 2006 International Conference on Communications,Circuits and Systems(第四届国际通信、电路与系统学术会议)

会议地点: 广西桂林

会议语种:英文

页码: 2498-2502

在线出版日期: 2006-06-25（万方平台首次上网日期，不代表论文的发表时间）