A New VLSI Architecture for Turbo Decoder Employing De-interleaver Table Free Method

摘要：

This paper presents a new interleaver and deinterleaver VLSI architecture for Turbo decoder. In our design, we propose a novel interleaving method, called Deinterleaver Table Free, which uses only the interleaver table to perform interleaver and de-interleaver. With this improved methodology, we can use only half size of two-port RAM to implement, as extrinsic memory will read and write in same sequence. This new architecture can remove de-interleaver table and provide 50％ of extrinsic memory bits reducing. Finally, we have designed a turbo decoder with TSMC 0.18μm 1P6M technology for demonstrating the architecture of the deinterleaver table free. The chip occupies 1.8 × 1.8mm2, consumes 54.64mW and supports 13.03Mbps decoding speed in 6 times of iteration.

作者: Wen-Ta Lee Jian-Liang Ye Yuh-Shyan Hwang Jiann-Jong Chen

作者单位: Institute of Computer and Communication National Taipei University of Technology Taipei, Taiwan Department of Electronic Engineering National Taipei University of Technology Taipei, Taiwan

会议类型: 国际会议

会议名称: 2006 International Conference on Communications,Circuits and Systems(第四届国际通信、电路与系统学术会议)

会议地点: 广西桂林

会议语种:英文

页码: 2524-2527

在线出版日期: 2006-06-25（万方平台首次上网日期，不代表论文的发表时间）