SystemC Transaction Level Modeling and Verification of IEEE 802.15.3 MAC
As implementation technology has evolved into increasingly complex integrated circuits and time-to-market pressure increases day by day, system level design issues become more critical in the context of system on Chip, which gives rise to the need for abstract executable specifications (models) covering both hardware and embedded software. The new capabilities of SystemC 2.0, such as those added for transaction-based communication and test-bench specification and monitoring, facilitate this SoC modeling. In this paper, we present a transaction level modeling and verification method of IEEE 802.15.3 MAC chip based on SystemC 2.0, which include an accuracy video model and a transaction level system model of IEEE 802.15.3 MAC protocol. With the proposed scheme, we can get a reusable test bench which can be used at both transaction level and register transfer level. In this case, the verification efficiency and accuracy will be greatly improved.Specially, the transaction level model can significantly reduce product development risk while avoiding expensive over-engineering by ensuring the architecture meets all performance, power and cost requirements prior to implementation, allowing design resources to focus on valueadded functions.
Yu Wei He Guanghui Xu Ningyi Zhou Zucheng
Department of Electronic Engineering Tsinghua University Beijing, China
国际会议
2006 International Conference on Communications,Circuits and Systems(第四届国际通信、电路与系统学术会议)
广西桂林
英文
2554-2558
2006-06-25（万方平台首次上网日期，不代表论文的发表时间）