Low-Power Content Addressable Memory Using 2N-2N2P Circuits

摘要：

In this paper, we presents a novel low power adiabatic content-addressable memory (CAM). It consists of a CAM-cell array, address decoders, read/write control circuits, sense amplifiers, read/write drivers and compare circuits. An AC power supply is used for driving the match-lines to reduce the energy consumption in adiabatic manner. The rest circuits employ 2N-2N2P circuits to recover the charge of node capacitances on address decoders, bit-lines and word-lines. The power consumption of compare operation is significantly reduced because the energy transferred to the capacitance buses is mostly recovered. The energy and functional simulations of a 16×16 CAM are performed. SPICE simulations indicate that the proposed CAM attains energy savings of 60％ to 80％ as compared to the conventional CMOS implementation for clock rates ranging from 25 to 200Mhz.

作者: Wu Yangbo Hu Jianping

作者单位: Faculty of Information Science and Technology Ningbo University Ningbo 315211, P.R. China

会议类型: 国际会议

会议名称: 2006 International Conference on Communications,Circuits and Systems(第四届国际通信、电路与系统学术会议)

会议地点: 广西桂林

会议语种:英文

页码: 2657-2661

在线出版日期: 2006-06-25（万方平台首次上网日期，不代表论文的发表时间）