A Wrapper for Low-Power Error-Correcting Data Delivery in On-Chip Networks

摘要：

Network-on-chip (NoC) design provides designers a communication infrastructure to integrate heterogeneous intellectual property (IP) cores. To reuse IPs based on shared buses in the NoC architecture, an interface is needed for the NoC communication protocol. In this paper, we present a wrapper design for low-power error-correcting data delivery in on-chip networks. Our wrapper not only provides an interface for reusing IP cores based on the AMBA bus, but also lowers down power dissipation and improves robustness of data transmission. We have implemented this IP wrapper using cell-based design with UMC 0.18μm technology. It shows that the wrapper design is feasible and efficient.

作者: Chia-Ming Wu Hsin-Chou Chi Ying-Ming Huang

作者单位: Department of Computer Science and Information Engineering National Dong Hwa University Hualien, Taiwan

会议类型: 国际会议

会议名称: 2006 International Conference on Communications,Circuits and Systems(第四届国际通信、电路与系统学术会议)

会议地点: 广西桂林

会议语种:英文

页码: 2662-2666

在线出版日期: 2006-06-25（万方平台首次上网日期，不代表论文的发表时间）